1. Field of the Invention
The present invention relates to a semiconductor memory and a method for manufacturing the same. More particularly, the present invention relates to a semiconductor memory whose yield is improved and a method for manufacturing the same.
2. Description of the Related Art
A nonvolatile memory (a flash memory) is known which has a nonvolatile characteristic that once stored information data is not deleted even if power supply is turned off unless deletion or write is performed. In the reading operation, the nonvolatile memory reads data by applying predetermined voltages to terminals of a memory cell and a reference cell and comparing an output of the memory cell with that of the reference cell by a sense amplifier.
FIG. 1 is a schematic view showing a configuration of a conventional nonvolatile memory. The nonvolatile memory 101 includes a plurality of main cell arrays 107-1 to 107-m (m is an integer of 2 or more), a plurality of sense amplifiers 105-1 to 105-m, a plurality of spare sell arrays 117-1 to 117-2, a plurality of spare sense amplifiers 115-1 to 115-2, and a reference cell 113. Other conventionally-known configurations not directly related to the present invention are omitted in this figure. Hereafter, when differentiation is not necessary, the numeral suffix portion (-numeral) among symbols in the configurations, such as “-1” and “-m”, is omitted.
Each of the main cell arrays 107-1 to 107-m includes a plurality of memory cells for storing data in a nonvolatile state. For example, each main cell array includes a plurality of bit lines and a plurality of flash memories placed along each of the bit lines. Each of the sense amplifiers 105-1 to 105-m is provided correspondingly to each of the main cell arrays 107-1 to 107-m. 
Each of the spare cell arrays 117-1 to 117-2 is provided as a spare of the main cell arrays 107-1 to 107-m, and includes a plurality of spare cells prepared as spares of the memory cells. Each of the spare amplifiers 115-1 to 115-2 is provided correspondingly to each of the spare cell arrays 117-1 to 117-2.
The reference cell 113 is provided as common use for the main cell array 107 and a spare cell array 117, and stores a reference data in a nonvolatile state. The data is used as reference for the reading operation of the data for the main cell or the spare cell.
In the case of the inspection in manufacturing steps, when a defect occurs in one of the memory cells in the main cell array 107, the main cell array 107 is recognized as a defective product. Then, the main cell array 107 is replaced with a spare cell array 117. In this case, a set of the main cell array 107 and the sense amplifier 105 are replaced with a set of s spare cell array 117 and a spare sense amplifier 115. Even if a defect occurs in the main cell array 107, it is not necessary to reject the whole semiconductor memory.
When the number of output bits is small, the number of the sense amplifiers 105 is the same as that of the output bits for the reading operation. In this case, a flash memory cell similar to a memory cell is used as the reference cell 113 for generating a reference data. The reference data is used for sensing the data in a memory cell. The reference cell 113 is connected to each sense amplifier 105 and shared by the main cell arrays 107.
However, when a high-speed reading operation is necessary, such as a page-read operation and a burst-read operation, it is necessary to previously read the cell data necessary for a data transfer time. Therefore, it is necessary to increase the number of the sense amplifiers 105. That is, the number of the memory cells in main cell arrays 107 is decreased to relate the increased sense amplifiers 105 to these main cell arrays 107. In this case, it is necessary to increase the number of the reference cells 113 correspondingly to the number of the sense amplifiers 105 in order to correspond to high-speed reading operation.
FIG. 2 is a schematic view showing another configuration of a conventional nonvolatile memory. The nonvolatile memory 101a includes a plurality of main cell arrays 107-1 to 107-n (n is integer of 2 or more; n>m), a plurality of sense amplifiers 105-1 to 105-n, a plurality of reference cells 103-1 to 103-n, a plurality of spare cell arrays 117-1 to 117-2, a plurality of space sense amplifiers 115-1 to 115-2, and a plurality of reference cells 113-1 to 113-2. Other conventionally-known configurations not directly related to a reference cell of the present invention are omitted.
Each of the plurality of the reference cells 103-1 to 103-n is provided correspondingly to each of the plurality of the sense amplifiers 105-1 to 105-n. Each of the plurality of the reference cells 113-1 to 113-2 is provided correspondingly to each of the plurality of the spare sense amplifier 115-1 to 115-2. Other configurations are the same as those in FIG. 1.
In FIG. 2, the number of the memory cells of the one main cell array 107 decreases and the number of the main cell arrays 107 increases. That is, the number of the memory cells corresponding to one sense amplifier 105 decreases. Moreover, the reference cells (103 and 113) are provided correspondingly to the cell arrays (107 and 117). By using this configuration, it is possible to treat the high-speed reading operation.
FIG. 3 is a flowchart showing the outline of inspection and replacement method in manufacturing steps of a conventional nonvolatile memory.
In the step S101, the reference cell 103 is evaluated. The evaluation is performed based on whether the nonvolatile memory succeeds in a predetermined writing, reading, and erasing operations of the reference cell 103. As a result of the evaluation, when the reference cell 103 has no problem (the step S101: OK), the step S102 is started. In the step S102, the evaluation is applied to all main cell arrays 107. Here, in each main cell array 107, all memory cells in the main cell array 107 are evaluated. The evaluation is performed based on whether the memory cell succeeds in a predetermined writing, reading, and erasing operation. As a result of the evaluation, when all memory cells in all main cell arrays 107 have no problem (the step S102: OK), the nonvolatile memory passes the inspection. When a defect occurs in one of the memory cells in the main cell array 107, that main cell array 107 is rejected (the step S102: NG). In this case, in the step S103, the defective main cell array 107 is replaced with the spare cell array 117 and the nonvolatile memory passes the inspection.
However, when the reference cell 103 has a problem in the step S101 (the step S101: NG), the inspection result is “failure” and the nonvolatile memory cannot be used because it is defective. That is, the yield of the manufacturing the nonvolatile memory becomes low. In this case, when the reference cells are defective, it can be estimated that main cells, of which the number is larger than that of the reference cells, are defective according to a probability theory. Therefore, when the reference cell has a defect in the process described in FIG. 3, it is not a problem to determine that the nonvolatile memory itself also has a defect.
However, in the case of the nonvolatile memory 101a in FIG. 2, because many reference cells 103 are used, the defective reference cells 103 do not always correspond to defective main cells in the main cell array 107. Particularly, in recent years, the number of sense amplifiers increases in a nonvolatile memory because of applying a multivalued cell in which a plurality of data are written in. The number of reference cells is further increased in accordance with increase of the number of sense amplifiers. Therefore, having defects on reference cells does not always mean having defects on main cells in a main cell array. Under the above condition, regarding a defective reference cell as a defective nonvolatile memory extremely lowers the yield of nonvolatile memories. A technique is desired which restrains lowering of the yield of nonvolatile memories due to defective reference cells.
In conjunction with the above description, Japanese Laid Open Patent Application JP 2001-184858 A discloses the following an integrated memory. The integrated memory has memory cells, reference cells, redundancy memory cells, and an activation unit which can be programmed. The memory cells are provided to the intersections between word lines and bit lines. The reference cell is provided to the intersection between at least one reference word line and a bit line, which is used to form a reference potential on the bit line before accessing one of memory cells. The redundancy memory cell is provided to the intersection between a redundancy word line and the bit line. The redundancy word line and the redundancy memory cell connected to the redundancy word line are replaced with the word line and the memory cell connected to the work line or replaced with the reference word line and the reference cell connected to the work line, based on the program status of the activation unit.